资源列表
lwip
- 本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上
lcd_1602_v
- 在quartus环境下，通过verilog 语言实现lcd1602 显示的程序-In quartus environment, through the verilog language lcd1602 display program
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
3_8_decoder_20170407
- 一个简单的38译码器程序，内附真值表，在本实验例程程序中用于Cyclone 2。(A simple program for 38 decoder.)
UartSend
- 基于ACTEL的FPGA的串口发送驱动程序。(ACTEL based FPGA serial port driver.)
FPGA_实时时钟设计
- 通过配置DS1302芯片来实现实时时钟的监测，我们通过通过控制2个按键来选择我们要在数码管上显示的时间，按下按键1我们来显示周几，按下按键2来显示年月日，不按显示时分秒，这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Pres
memory生成和接口说明
- memory生成结构说明文档；使用Verilog语言(Memory generated structure descr iption document)
Example25
- 设计一款基于VHDL的数码锁的小程序，其中加入了数码管显示功能及报警系统-VHDL-based design a digital lock small program, which joined the digital display and alarm system
求最大公因数（vhdl）
- 利用fpga设计一个系统求两个数的最大公因数。数字系统设计：控制路径和数据路径。
RTL
- 用VHDL实现求两个数的最大公因数。数据路径和控制路径。-Seeking to use VHDL to achieve the greatest common factor of two numbers. Data path and control path.
EP1C3_71_SINGT
- 这是一个描述的vhdl语言描述，请大家下载啊-This is a descr iption of the vhdl language descr iption, please download ah
PWM_LED
- 该程序利用ISE软件实现了FPGA控制的PWM波形的发出，给了一个简单的算法，频率可调-The program utilizes the ISE software FPGA to control the issue of PWM waveform, and gave a simple algorithm, frequency adjustable