资源列表
jiaocheng
- 该文档描述了数字系统下的各种设计实验的原理及其源代码-This document describes a variety of digital system design principle of the experiment and its source code, etc.
EDACLOCK
- 一份关于EDA设计数字时钟的报告，与大家分享，希望对大家有帮助-EDA design of a digital clock on the report, to share, we want to help
verilog_DA_TLC5615
- verilog 写的硬件示波器设计检测频率为1K~10KHz-verilog 1K~10KHz test
verliog_VGA
- verilog实现 VGA视频输出 ：直接输出到CRT，场频60，行频36-verilog to vga
verilog_16_SRAM
- 一个很好的Verilog测试sram程序-Verilog test sram
exp_cpu_vhd
- cpu模型，除了时序和显示模块，有两个warning-A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows --a right execution of computing. --ZHANG Hongjie 2010.6.11 -- Warning: Inf
MSP430C
- 用FPGA实现JPEG的Verilog源代码-JPEG with the FPGA implementation of the Verilog source code
UART
- A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
ftdd
- 在fpga中实现demosaicing的功能-Implemented in fpga function demosaicing
2BCD
- 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过 所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
anjianshumaguan
- 按键与数码管显示 采用verilog语言编译 可在quarter ii编译 所有文件都包含了-Buttons and digital display with verilog language compiler can be compiled in the quarter ii files contain all