资源列表
uart_rar_testbenchfidsof
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
verilog_uart_log_vhdl_uart_logfdj
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
verilog_uart_log_vhdl_uart_log
- verilog uart mode code VHDL uart mode -verilog uart mode code VHDL uart mode code VHDL uart mode
jiaotongdeng
- 使用quartus2实现的交通灯控制，包括各个模块实现及总体实现-traffic light
soft_demapper
- This is soft demapper algorithm
ANSWER
- 采用VHDL设计的抢答器，抢答时间10秒钟，10秒内无人抢答，则抢答按键失效。显示抢答的队伍号。适合做课程设计。-Design using VHDL Responder, Responder for 10 seconds, no answer in 10 seconds, then the answer in key failure. Display answer in team numbers. Suitable curriculum design.
SONGYFQ
- 用VHDL设计的电路，输出接到喇叭可播放乐曲“一分钱”。适合做课程设计。-Circuit design with VHDL, output to speakers can play music, " a penny." Suitable curriculum design.
messageschedule
- Para calcular las palabras de cada ronda del algoritmo SHA
Design-of-general-purpose-registers-vhdl-language.
- 寄存器设计，以VHDL语言设计模拟一个通用寄存器。可供初学者学习。-Register is designed to simulate a VHDL language design general-purpose registers. For beginners to learn.
cdngo
- MP3 Code Converter program
lab
- VHDL Lab manual useful for experiment purpose
VERILOG_VLSI_LAB_MANUAL
- VHDL Lab Manual useful for lab purpose