资源列表
RS232
- 此代码已在实验板上验证，波特率9600，时钟50MHz。-This code has been verified in the experimental panel, 9600 baud, clock 50MHz.
spilicheng
- spi接口的wishbone总线的实现，能够实现spi控制器的基本功能，书上例程-spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine
FPGA-TOP-TOWN
- FPGA/EPLD的自上而下（Top-Down）设计方法-FPGA/EPLD ( Top-Down ) top-down design method
FLASH_16PWM
- C8051F340开发PWM程序，希望对大家有帮助。-The C8051F340 developed PWM program, we hope to help.
UART0
- C8051F340开发UART程序，希望对大家有帮助。-The C8051F340 developed UART program, we hope to help.
UART0_ADC
- C8051F340开发UART&ADC程序，希望对大家有帮助。-The C8051F340 developed UART&ADC program, we hope to help.
sy5
- 移位寄存器 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) --来自0809转换好的8位数据 CLK : IN STD_LOGIC --状态机工作时钟 EOC : IN STD_LOGIC --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC --8个模拟信号通道地址锁存信号 START
EMP7128S
- EMP71285 CPLD实现三通道24位计数器，程序为.VHDL语言实现，同时程序中含有低通滤波算法。-EMP71285 CPLD implementation of three-channel 24-bit counter, the program for the VHDL language, the program contains a low-pass filtering algorithm.
200811525
- 学习Quartus II、SOPC Builder、Nios II IDE的基本操作。 初步了解SOPC的开发流程，基本掌握Nios II软核的定制方法。 掌握Nios II软件的开发流程，掌握软件的基本调试方法。-Study of Quartus II, SOPC Builder, Nios II IDE of the basic operation.A preliminary understanding of the SOPC development process, to mast
8255_1
- It is about the VHDL code of 8255 and it has got the code of it. SO please enjoy
verilogdiv_3_5_7
- verilog写的奇数分频，适合初学的同学分析，容易上手，已测试。-verilog to write the odd divider, suitable for beginner students, easy to use, have been tested.
fpga-pll
- cyclone的pll应用，精确翻译，适合需要又不想看英文文献的同学。-cyclone the pll applications, accurate translation, suitable for students of English literature need not want to see. Undo edits Dictionary