资源列表
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
ug_avalon_verification
- Avalon Verification IP Suite verification userguide
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
16QAM
- 详细介绍了16QAM的fpga实现过程，并通过verilog语言编程，可以得到比较好的效果-Details the the the 16QAM fpga implementation process, and can get better results through the verilog language programming,
RGB-to-yuv422
- verilog语言写的视频数据处理相关的代码。实现功能为将RGB数据转化为BT656数据。-verilog language to write video data processing related to the code. Functions for the RGB data into the BT656 data.
fenpin
- 从50MHz的内部时钟通过此程序分频得到1Hz时钟，改变参数还可以有其他的频率- frequency division
CPU-project
- 硬件实验 设计一个给定指令系统的处理器 支持多条指令带进位和不带进位的ADD，SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,清零等等，内有设计报告-Hardware experiment，design a CPU with the command following:SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,clear, and so on.There is a disigning report in it.
vga_juxing
- 源码要求为至少5个C或Java源码或其他好源码或编程学习资料源码要求为至少5个C或Java源码或其他好源码或编程学习资料-vhdl of mansiter are you ok understandvhdl of mansiter are you ok understand vhdl of mansiter are you ok understand vhdl of mansiter are you ok understand vhdl of mansiter are you ok unders
Performance-Analysis-of-(63-56)-Bch-Code-Using-mu
- BCh code for error correction contro-BCh code for error correction controll
serial
- 用VHDL测试代码进行存储器读写测试，使用元件例化的方法-experiment of visiting SRAM using the means of components
RSCode_XuChaojun
- 徐朝军的博士论文，详细的介绍了RS编码解码算法以及进行了性能分析。-Doctor paper from Xu Chaojun . A detailed descr iption of RS encoding and decoding algorithms and performance analysis
01_PlanAhead
- planahead fpga 设计视频介绍-1-planahead fpga design demo-1