资源列表
carLights-prelab
- vhdl sample of car lights which is a good example code for beginners for vhdl
fifo
- frist in frist out in pdf format
AES
- AES implementation in VHDL@!
FPGA_VHDL_exambles
- FPGA的27个VHDL实例,包括源程序和仿真程序，是初学者的好材料。-27 FPGA VHDL examples, including source code and simulation procedure is a good material for beginners.
fft_256
- 256点的fft，使用verilog硬件描述语言实现，可以在quartus等仿真软件仿真-failed to translate
an490
- Altera官方网站提供的MAXII系列CPLD做电平转换的应用文档，非常实用的。-Official website of the MAXII Altera CPLD family to do the application-level document conversion, very practical.
vhdluartmode
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
uart_rar_testbench
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
Altera_FPGA_CPLD_Designing(Advanced)
- Altera FPGA_CPLD设计(高级篇) Altera FPGA/CPLD学习的优秀参考书-Altera_FPGA_CPLD_Designing(Advanced)
Goldenguid_Verilog
- Verilog黄金指导（中英文版本）,费了好大劲才找到，发扬共享精神~-Verilog Golden guidance (in English), take a great job finding and carry forward the spirit of sharing ~