资源列表
DE2EP2C35F672
- DE2 EP2C35F672d的管脚分配图-DE2 EP2C35F672d pin allocation map
washer
- 本人用verilog HDL写的一个洗衣机工作流程。由于是第一次写，难免很多不足~多多指教.-well ,this is a verilog project which describes a washer machine.
MIDIsynthesisalgorithmanditsFPGAimplementation
- MIDI合成算法及其FPGA实现MIDI synthesis algorithm and its FPGA implementation-MIDI synthesis algorithm and its FPGA implementation
jiaotongdeng
- 基于EDA技术交通灯控制器verilog程序代码-Traffic signal controller based on EDA technology verilog code
vhdlprograms.tar
- multiplexer 4 to 1... for 4 inputs. decoder.... counter alu mod16
song
- 使用Qutus下载后可在硬件上实现乐曲《友谊地久天长》-Use Qutus download music in the hardware realization of " Auld Lang Syne"
VHDL1
- 七段数码管显示器，显示从0到9十个数字，上传供大家分享。-Seven-Segment LED display, showing the ten numbers from 0 to 9, upload for everyone to share.
b
- 递归下降分析器的设计 首先将文法改写成EBNF形式，根据递归下降分析法基本思想编写程序。 -The design of recursive descent parser rewrite first EBNF grammar forms, according to the basic idea recursive descent analysis programming.
jiaotongled
- 该源码用vhdl语言制作了一个简单的交通灯，方便大家学习-The source vhdl language produced by a simple traffic light, facilitate learning ~ ~
matlab-jiaocheng
- matlab教程，Matlab5.0手册上下-matlab tutorial, Matlab5.0 manual up and down
FPGAarchitecturedesign8bi_CISCCPU
- FPGA架构的8位CISCCPU设计FPGA architecture design 8-bit CISCCPU-FPGA architecture design 8-bit CISCCPU
shumaguan
- 用按键控制选择6进制和9进制加法器，并用数码管显示。-Select 6 with keypad control, binary adder binary and 9, and with digital display.