资源列表
verilog_PLL
- verilog 写的硬件 pll 锁相环实现-verilog to pll
debounce
- push button program that take 20ms afther that it load data
fir_compiler
- FIR编译器。自动生成具有用户自定参数的FIR滤波器。 在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。 -FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl
src
- FIR滤波器的设计，完整包括RTL代码、testbench等，清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
01chufaqi
- 带同步清0、同步置1 的D 触发器 verilog语言描述的-0 with synchronous clear, synchronous set 1 D flip-flop verilog language descr iption
qiduanshumaguandongtaixianshi0000-9999
- 七段数码管动态显示 采用vhdl语言设计 编译 已通过-Seven-Segment LED dynamic display design using vhdl language compiler has passed
du
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
xie
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
shuzishizhong
- 用VHDL实现的数字时钟，源代码以调通，能够直接使用！-VHDL implementation of serial communication with the source code to adjust pass, can be used directly!
VGA_TEST
- 用verilog HDL实现的VGA接口，调试成功，能直接使用-Implemented using verilog HDL VGA interface, debugging success, can be used directly