资源列表
SOPC_watch
- 基于ALtrafpga的niosii内核verilog语言实现的可编程电子钟，需要外接lcd屏幕-Programmable electronic clock, based on the the ALtrafpga the kernel niosii verilog language to achieve an external lcd screen
27072158834900
- 使用FPGA进行北极光设计，非常漂亮的小制作。使用VERILOG HDL语言-Using FPGA design northern lights, very nice production. VERILOG HDL languages
signal_generator
- 信号发生器的FPGA实现，能输出正弦信号，方波信号，三角波信号-FPGA implementation of the signal generator can output a sinusoidal signal, square wave signal and triangular wave signals
verilog
- 实现1602的显示，实
dac7621
- dac7621数模转换驱动，使用verilog语言写的。-dac7621 digital to analog conversion drive
ads831
- ADS831模数转换驱动，使用verilog语言写的。-ADS831 analog-digital conversion drive, write verilog language.
pwm
- 乒乓球实验的VERILOG源代码。XILINX spartan6.-Table Tennis experiment VERILOG source code. XILINX spartan6.
pingpang
- 500分频的verilog源代码。XILINX SPARTAN6.-500 divided by the verilog source code. XILINX SPARTAN6.
vga
- VGA显示的verilog整个代码。在xilinx spartan6板子上测试。-VGA display the verilog source code. Test in on xilinx spartan6 board.
10beipin
- cpld的10倍频程序，并进行功能仿真。-the cpld decade program, and functional simulation.
7_seg
- 七段显示译码器完整程序，适用芯片Cyclone 2系列-Segment display decoder complete the program, applicable to chip the Cyclone series
verilog_dds
- verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series