资源列表
verilog--uart
- verilog实现uart功能的FPGA应用，适用于Cyclone 2系列-verilog uart function of FPGA applications in the Cyclone Series
verilog--sram
- ram的fpga应用，用verilog语言实现，适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
10_100m_ethernet-fifo
- 本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。-The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion.
vhdl_can_IP.tar
- 运用VHDL语言实现的一个CAN通信控制器IP核-Communication of a CAN controller IP core using VHDL language
can_verilog_IP.tar
- 运用Verilog语言编写的CAN控制IP核，符合CAN2.0B协议，仅作为参考！-CAN controller IP core using Verilog language, in line with CAN2.0B agreement, only as a reference!
i2c_latest.tar
- IIC通信机制的Verilog HDL实现，IIC是一种串行通信总线，它可以提供为设备间的通信提供一种简单有效的方式-IIC communication mechanism of Verilog HDL implementation, I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices。
most_latest.tar
- MOST总线是被广泛被应用于车载媒体数据传输的总线，本源码采用verilog语言编写了其控制器，其特点是具有很高的用户可定制性。-MOST bus is to be widely used in car media data transmission bus, the source verilog language of its controller, which is characterized by high user customization.
simple_spi_latest.tar
- - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC6
xiaqdq
- 基于FPGA的4路抢答器VHDL源代码，完整工程-4-way Responder based on FPGA VHDL source code
bjq
- 基于FPGA的半加器，完整工程及代码，已测试-FPGA-based half-adder, full engineering and code
fpq
- 基于fpga的分频器设计，完整代码及工程-Fpga-based crossover design, the complete code and engineering
ipfp
- 基于fpga的分频器设计，利用ip核做的，完整工程及代码-Fpga-based crossover design, using the ip nuclear, complete engineering and code