资源列表
TLV5618
- TLV5618可编程双路12位数模转换器产生三角波正弦波-The TLV5618 Programmable Dual 12-bit DAC and the triangle sine wave
TLV5639
- tlv5369 12位da输出4个控制位12个数据位-tlv5369 12 da 4 of the output control 12 data bits
mulx
- FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
3_to_8
- 三八译码器，开发环境是quartus ii，虽然编码简单，不过还可以-Thirty-eight decoder development environment is quartus ii, simple encoding, but can also
random
- 随机数产生以及发牌程序 包括test的tb程序-Random number generator and licensing procedures, including test
EDK_Microblaze
- 很好的EDK学习资料，全中文教程，一步步教你怎么使用Microblaze生成嵌入式软核。-Good the EDK learning information, and the whole Chinese tutorial, a step by step to teach you how to use the Microblaze generate embedded soft core.
led_seq_demo
- 跑马灯的打包verilog程序，包括v和ucf,以及能直接下载的xise文件-The Marquee verilog program package, including v and ucf, and can be downloaded directly xise file
frequency-meter
- 开发环境是quartus ii，是学校的一个FPGA实验，计算一个信号的频率，这个是我做得最好的一个作品，调试成功。压缩包里包含题目要求以及我做好的模块。-Development environment is quartus ii, an FPGA experimental school, calculate the frequency of a signal, this is I' m doing the best work, debugging success. The compres
write1
- 串行接口发送，通过绑定DE2上的拨码开关，然后通过RS232接口传送到pc上，可通过串口调试大师接收数据-Serial interface to send, through binding DE2 DIP switch, and then transmitted via the RS232 interface to the pc, can receive data through the serial debug master
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
I2C
- 基于verilog的I2C代码，包含master和slave两个模块-Verilog-based I2C code that contains the master and slave two modules
RISC_CPU
- 基于verilog的risccpu实现，只有一个指令，对于了解risccpu的工作原理很有帮助。-Based on verilog of risccpu, only one instruction, helpful for understand risccpu works.