资源列表
crc_tool
- 用c编写的自动生成并行crc处理的verilog代码的工具-Automatically generate the verilog code to parallel crc processing tools written with c
agc
- 无线通信中接收侧自动增益控制模块的vhdl代码实现-Receive side of the AGC module vhdl code for wireless communications
cic-1
- cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch
multiplier
- 8*8的乘法器基于quartus2的显示文件，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，由于是第一次上传文件，这个是基于quartus2的显示文件-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
EX28_CPLD
- Quartus编程环境下，DSP5509与CPLD的通信过程，用VHDL来编写的。-The connection between DSP and CPLD
multiplier
- 8*8的乘法器，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
add
- 16位的加法器，全加器，有效的利用了门电路用以实现全加器的进位-16 of the adder, full adder and effective use of the gate for the binary full adder
120606003
- count program written by verilog code
huanxingfenpeiqi
- 步进电机的环形分配器，VHDL文件源码，经编译全通过，没有仿真，-Annular distributor of the stepper motor, VHDL file source, compile the whole through, there is no simulation.
ultrasonicmeter
- ultrasonic meter with srf04 with 7 segments display
multiplier
- 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
adder
- adder in verilog only with combinational logic use