资源列表
ps2
- 基于ps2类型接口的键盘控制程序，并且在数码管上显示按键的内容-Ps2 type keyboard interface control program, and display the contents of the keys in the digital pipe
sccb
- 基于数字摄像头在初始化的时候的一种协议，包含时钟线和数据线。-Based on a protocol of the digital camera in the initialization time, including the clock and data lines.
stopwatch-shuzipabiao
- 在FPGA下实现分频、计数、显示功能。 数字跑表-Divider in FPGA, counting and display functions. Digital stopwatch
state_machine
- 一个用VHDL实现的基于FPGA的简单的状态机程序-A VHDL implementation of FPGA-based simple state machine program
decimetion
- 攒人品上传多年工作积累代码。主要功能是adc 的多阶后续数字滤波器，等控制。可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to adc the multi-order follow-up digital filter control. Can be integrated.
ddr_ctrl
- 攒人品上传多年工作积累代码。主要功能是ddr memery controler interface等控制。可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to ddr memery controler interface control. Can be integrated.
osd
- 攒人品上传多年工作积累代码。主要功能是OSD图形控制的代码。经过验证，可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to control the OSD graphics code. Proven, can be integrated.
rgb2yuv
- 攒人品上传多年工作积累代码。主要功能是RGB到YUV转化的代码，可以芯片综合。-Save the character to upload the accumulation of many years of working code. The main function of the RGB to YUV conversion code, you can chip integrated.
vds_proc
- 某知名外企公司解禁verilog代码。主要功能是视频显示处理等控制。可以综合。-A well-known foreign companies lifted the verilog code. The main function is the video display processing and control. Can be integrated.
infmt
- 攒人品上传多年工作积累代码。主要功能是对视频输入信号的滤波等控制。可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to control video input signal filtering. Can be integrated.
scaler
- 攒人品上传多年工作积累代码。主要功能是对视频信号格式的变化大小等处理。可以综合.-Save the character to upload the accumulation of many years of working code. The main function is to deal with changes in size of the video signal format. Can be integrated.
16mult_signed
- 16*16位的有符号乘法器的verilog语言-16 x 16 signed multiplier verilog language