资源列表
FSK-VHDL
- 基于VHDL硬件描述语言，对基带信号进行FSK调制-VHDL hardware descr iption language based on FSK modulation baseband signal
8051core-Verilog
- C51 verilog 源代码，可以在逻辑中实现51单片机功能-C51 verilog
LCD12864_ST7920
- LCD12864驱动程序 可实现以ARM为CPU的LCD12864的驱动-LCD12864 driver enables ARM-CPU of LCD12864 drive
love
- 用数码管和LED等来显示心形的LOVE，可以送给女朋友的 哦-LOVE heart-shaped digital control and LED display, can be given to a girlfriend
usb_jtag-20070128-1751
- 网上流传的usb_blaster原理图里的CPLD源码,主要是实现usb时序转换成JATG时序输出！-spreading online usb_blaster tenets of the CPLD Ituri source, usb key is timing converted into JATG sequential output!
8051IPcore，verilogHDL实现
- 用verilog写的很好的cpu core-using Verilog write a good cpu core
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
JH
- JH算法是第三代安全HASH算法最终入选算法之一，这里是它的完整VHDL实现-JH is one of the the final SHA3 algorithms, this is the whole VHDL implementation of JH.
FPGAExamples
- 列举了一些FPGA的常用实例，有助于加深对FPGA的了解-gfdhgfhgfdgvfhgfhgjngh
Organprogramdesignandsimulationwithvhdl
- 电子琴程序设计与仿真。包括顶层程序与仿真，音阶发生器程序与仿真，数控分频模块程序与仿真，自动演奏模块程序与仿真。-Organ program design and simulation. Including the top-level procedures and simulation, scale generator, procedures and simulation, numerical control program and simulation of frequency module,
spi_inf_middle_filter
- 采用spi接口读取adc数据，存储数据，将数据进行中值滤波处理，最后通过总线接口发送到dsp处理器-spi interface adc sample program with middle filter process.
FPGA_CycloneII_EP2C5_EP2C8
- cycloneII ep2c5 ep2c8