资源列表
SDH_module
- SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
jiaotongdeng
- 实现交通灯，定时循环，不断轮换，黄绿红间断闪亮-Traffic Light
MUX_4_8
- 4通道8位带三态输出,以及经过验证确实可用，大家可以放心下载-4 channel 8 bits with tri-state outputs
verilogHDL03
- VerilogHDL硬件描述语言之3
vhdl
- 用FPGA实验台下载实现的简易电梯控制系统，-FPGA test-bed with a simple download to achieve the elevator control system,
Xilinx-Configuraon-Reference-
- 本应用笔记讨论的是Xilinx 的复杂可编程器件（CPLD）、现场可编程门阵列（FPGA）和PROM系列的配置和编程选项。它示意了每个系列的最常用的一些配置方法。-This application note of the discussion is the complex programmable device Xilinx (CPLD), field programmable gates array (FPGA) and PROM series of configuration and pro
liushuideng
- 这是一个简单的流水灯VHDL程序，适合初学者-This is a simple VHDL program of light water, suitable for beginners
bcdadd
- 4-Bit BCD Adder in Verilog
coregen_tutorial
- core generator vhdl book
verilog_UART
- verilog语言 FPGA 串口收发模块，既可以接收也可以发送，可以自行更改波特率-Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
test
- PPM编码的VHDL实现，可实现8位并行输入数据转换为串行的PPM编码-PPM coded VHDL implementation can be realized 8-bit parallel input data into a serial coded PPM
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i