资源列表
Verilog_cpu-_example
- 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
UYYTY
- 一种关于高速时钟提取的文章，讲述了锁相环提取时钟的优缺点。
NEW-AD9954
- 一个开环的AD9954 的正弦波发生 verilog 程序。-An open loop of the AD9954 in the sine wave occurs verilog program.
电子钟clock
- 用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
clock
- 用VHDL语言写的实时时钟 用数码管显示 基于的控制芯片是EP1C6Q24C08-VHDL language used to write the real-time clock with digital display are based on the control chip EP1C6Q24C08
4bitCounter
- VHDL编写的四位加法计数器，可以通过QuartusII环境验证
fifo_2
- 一个关于FIFO的VERILOG程序。很不错的。-VERILOG a procedure on the FIFO. Very good.
clock
- verilog 实现的跑表程序。可以对这个程序加以修改，可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很！-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
qudou
- 此源代码为去抖动模块代码，代码简洁易懂，并已仿真成功，可以下载。-The source code for the debounce module code, the code easy to read, and has been successful simulation, you can download.
SPWM.rar
- 用cpld开发的关于生成spwm波的vhdl程序代码,Cpld developed by spwm waves on the generation of vhdl code
LCD
- 经典LCD显示程序，经过认证试验，确保无误。引脚说明等。-Classic LCD display program, certified test to ensure correct. Pin descr iptions.
CPLD
- CPLD编程，处理两路编码器的信号，可以将信号四倍频。同时能够控制IO的输入输出信号。-cpld program