资源列表
beep
- verilog语言来控制beep的程序!简明简单-verilog beep
dptaal
- Design of Adiabatic logic using VHDL
Altera_Quartus_SPI
- SPI on Quartus Altera witn testbensh simulation
hangci
- verilog写得频率记，专门测频率，在cpld上运行，epm240t1-verilog frequency note written specifically measured frequencies cpld run, epm240t100
vga
- 能够通过FPGA系统进行控制，由VGA接口在电脑显示器上显示横条，竖条和棋盘图形-FPGA systems through control of the computer monitor by the VGA interface to display bar, vertical bar and board graphics
vgaout
- VGA的程 序，可以显示红绿蓝三色在VGA-VGA program, you can display red, green and blue colors in VGA
A8251
- Altera Quartus Megacore of A8251 (UART). Published by Altera for free after the IP Megacore portfolio has changed.
tongyong
- 通用寄存器组中有1个写入端口，当DRWr=1时，在时钟clk的上升沿将数据总线上的数据写入DR[1..0]指定的寄存器。-General-purpose register group has a write port, when DRWr = 1 when the clk rising edge of the clock on the data bus write data DR [1 .. 0] specify the register.
demo9-vgaout1
- 一段VGA实验，适合初学者学习使用，非常实用，但如果要编写复杂图像显示，自己就需要再看些-A VGA test, suitable for beginners to learn to use, very practical, but if you want to write complex image display, and that they need to look more
si_xi_fen
- Quartus环境下，用verilog ＨＤＬ写的光电码盘的四细分程序，用于获得转向和转速-Quartus environment, use verilog HDL write light code disc four segmentation procedure, are used to obtain steering and speed
clock
- 多功能数字时钟设计的源程序,可以实现计时\闹钟\鸣笛等基本功能多功能数字时钟 可报时 调整时间-Multi-functional digital clock timekeeping adjustment time
1
- 微机原理与接口技术实验 交通灯 8255 8259 8253-Microcomputer Principle and Interface Technology Experiment traffic lights 825582598253