资源列表
csa2
- carry save adder block2
wallace_pp_hafa
- wallace tree,partial products,half adder and full adder
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
CPLD_FPGA
- 基于CPLD/FPGA的数字通信系统建模与设计，里面讲述了通信系统的VHDL建模和各种基本电路的建模与设计，在通信原理课程设计中一般会用到！-Based on CPLD/FPGA Digital Communication System Modeling and Design, which describes VHDL modeling of communication systems and a variety of basic circuit modeling and design, pri
VHDL
- 这介其中一个人人一个程序的设置时间为settime-settime for settime
danpianjixitongban
- 全国大学生电子设计竞赛单片机最小系统版-内含原理图、系统版等文档和图。-National Undergraduate Electronic Design Contest SCM minimum system version- includes schematics, system version and other documents and plans.
cam
- It is a VERILOG program for interfacing the 5Megapixel camera module in ALTERA DE2 CYCLONEII board.
FPGA-CPLD
- FPGA-CPLD开发教程.rar 开发fpga必看的书籍 可以参考着开发 作为不时之需-FPGA-CPLD Development tutorial. Rar fpga development can refer to the books must see development as a rainy day
61EDA_C2187
- Xilinx fpga 设计培训中文教程 xlinx环境下的-Xilinx fpga design training tutorial xlinx environment in Chinese
Helloworld
- Helloworld Programme in VHDL for SPartan-3E
invaders_rel0300
- Space invadors for Spartan-3E
SAP-processor-with-Test-Bench-working
- SAP processor in verilog with test bench complete and working