资源列表
ALUandControl
- 用verilogHDL编写的ALU功能实现以及控制信号的产生，还附有波形仿真测试的源文件-Written by verilogHDL ALU function realization and control signal generation, but also with a simulation test of the source waveform
VHDLTESTBENCH
- 本文档对编写vhdl的testbench具有很大的参考价值，偶那个多方面考虑的-The preparation of this document, the testbench vhdl of great reference value, even considering that many
LIP7101CORE_Handheld_Bike_Computer
- Handheld Bike computer verilog code
LIP6921CORE_decss
- Encry Decry DECESS verilog code
Synchronous-sampling
- 飞行试验同步采样规则，主要用于固态记录仪的研发-Synchronous sampling test flight rules, mainly for the development of solid-state recorder
LIP6911CORE_dct_4
- DCT Verilog source code
LIP6903CORE_CSC_RGB2YUV
- CSC RGB2YUV Verilog source code
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
song
- 当在CLK12MHZ输入12MH，在clk4hz输入4hz时，扬声器就会播放第一首《一生有你》，再经过按键1和按键2，可以选择其他三首歌曲，例如《隐形的翅膀》等 同时有个led显示高音调，一个数码管显示播放时的第几音调，一个数码管显示此刻播放第几首歌曲-When CLK12MHZ input 12MH, in clk4hz input 4hz, the speaker will play the first song, " life have you" , and then
9.59
- 实现9分59秒的记时功能 当输入1Hz的脉冲时，且START置1时，能正常记时，当将RESET置1时，可以实现复位功能 当将STOP置1时，可以停止记时，记时的能记到9分59秒-9 minutes and 59 seconds to achieve when the mind functions when the input pulse 1Hz, and START is set to 1, to normal mind, and when the RESET is set to 1 w
runhouse
- vhdl实现跑马灯的功能，(*^__^*) -vhdl function ,(*^__^*) achieve Marquee hee hee ... ...
watch
- 本文件为电子设计而开发的多功能数字钟VHDL语言完整源代码 --该数字钟实现的功能有时间，秒表，闹钟，年月日的显示设置等 -This document is multi-functional electronic design and development of a complete VHDL, digital clock source code- the digital clock function can be achieved time, stopwatch, alarm clo