资源列表
17jieFIR
- 17阶FIR滤波器VHDL代码及说明文档-17-order FIR filter VHDL code and documentation
PXI_Module_Description
- PXI Module Descr iptionFile Specification PCI eXtensions for Instrumentation An Implementation of PXI Module Descr iption File Specification Rev. 1.0 9/25/2003 PXI-4 Revision 1.0
AT89C51PMAX7219pinlvji-
- 实现的是一个频率计的功能，源代码中分4各模块，各自实现自己的功能 最后综合起来实现频率计的功能-Implementation is a function of frequency meter, the source code of each module carve 4, each of the last to realize their functions together to achieve the function of frequency meter
aclock
- 一个verilog的经典实例,即智能化的数字钟-an example of verilog,a clock
FPGA
- ＦＰＧＡ学习资料 认真学习 一定要好好学习-FPGA learning materials have to learn to seriously study
Six-phase-Motor-Based-on-DSP
- 设计了六相感应电机的控还原 制平台的硬件结构及其各个组成部分,控制平台结构主要由DSP控制系统和主驱动电路系统以及检测电路系统组成。控制系统采用TI公司的TMS320F2812快速DSP控制芯片。 -This paper designs the hardware structure of the six-phase motor control system and introduces every component. The control platform consists
USB_SLAVE_700AN_RD
- 基于verilog 代码的USB2.0同步FIFO读代码-USB2.0 syn FIFO read
USB_SLAVE_700AN
- 基于verilog的USB2.0同步写操作代码-usb2.0syn write code
rtl
- 基于verilog的FPGA新型跑马灯程序设计-led run
thefirstexampleforQuartuslearners
- quartuslearners 学习 入门 软件应用-quartusII study
l2
- write the verilog code for the following specification & perform the linting checks
lab1
- labs in verilog it consists of lab work from design of mux adders from primitives