资源列表
CPU-design
- 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
vga_lcd_latest.tar
- vga code with descr iption in verilog
parite
- decode VHDL parite You can decode a parite on x bytes
Crack_QII_10.1_Windows
- quartus 10.1破解文件 内部人员用-quartus 10.1 crack file with internal staff
LCD
- 基于altera cyclone3芯片，quartus软件lcd显示-lcd display
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi
Verilog
- Verilog 教程，简单易学，通俗易懂，很值得推荐的，实验室用的，愿与大家分享-Verilog tutorial, easy to learn, easy to understand, it is recommended, laboratory, and is willing to share with you
vhdl
- 是VHDL的资料，很不错的代码，原创的。-VHDL data is very good code, and original.
multiplieur8
- 8 bits classique multiplieur
aditionanticip
- Additionneur 16 bits avec calcul anticipé des retenues
QuadratureCounter
- gdf example for Quadrature Encoder Counter
Counter-60
- In this example, counter 60 is implemented as part of the real time clock time electronic clocks. Done in the platform mentor Graphics and describes in the VHDL code. This counter has a role to the front edge of every 60 clock sends a signal followin