资源列表
LIP6421CORE_video_decoder
- Video decoder verilog source code
ADcaiyang
- 通过vhdl语言来实现ad的数据采集预处理-Vhdl language ad by the data acquisition to achieve pre-
cepinqi
- 通过哦vhdl语言来实现频率的测量和处理-Oh vhdl language to achieve by the frequency of measurement and processing
decoder3_8
- 通过vhdl语言来实现简单的3--8译码器的制作-Vhdl language to achieve through a simple 3- 8 decoder making
jiaotongdeng
- 通过使用vhdl语言来实现交通灯的设计与制作-Achieved by using vhdl language design and manufacture of traffic lights
serial_check
- 本实验需要实现一个序列检测器，用来检测输入的串行位流是否和程序设定的位串相一致，若一致则在验证波形的出现一个高电位来表示。本实验需要验证的位串是“101011”。-In this study, need to implement a sequence detector, to detect whether the input serial bit stream and procedures consistent set of bit strings, if the same occurs in
four-bit-mul
- 用加法器乘法树实现四位乘法器。绝对可以实现，大家不妨下来-Achieved with the four adder tree multiplier multiplication
coded-lock
- 设计的是一个保险柜的数字锁控制电路。首先最主要的问题是安全，也就是开锁的密码被破译的可能性要尽可能小；其次是操作方便，开锁的程序不过于复杂。此外还有一些特殊要求，例如可预置和更改密码，多次输入错误密码应启动报警系统，使用者在拨错号码时可将原拨号码清除重拨，段码显示等。-Design is a digital safe lock control circuit. First, the main problem is security, that is unlocking the password
max7000vgasync
- VHDL animation with simple codes
zlesson2BrA
- english for grammer fluency
61EDA_D506
- 一个dwt的 vhdl code，非常实用-dwt of vhdl code
SystemVerilog
- 几个systemveriog的例子，包括8-bit up counter和divide-by-2 counter-about systemverilog