资源列表
counter_4bit_code
- vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares-vhdl source code for a 4 bit counter to be use in active hdl and other vlsi softwares....
DE1-Practice-VGA-display-
- 用altera的fpga设计的DE1开发板作为硬件平台实现VGA显示，verilog实现的，8种色彩，作为fpga驱动vga液晶的入门。DE1实践之VGA显示（8bit色彩）-Altera fpga design with the DE1 board as a hardware platform development VGA display, verilog implementation, 8 colors, as the introduction to fpga driver vga LCD
ff_const_mul
- 常系数有限域乘法器，verilog DHL源码-Constant coefficient finite field multiplier, verilog DHL source
xilinxtestbench
- 适合编程开发人员阅读，xilinx编程测试文档编写指导-Programming for developers to read, xilinx programming and writing test guide
iic_verilog
- iic 程序 用verilog语言编写，可以直接使用-iic program using verilog language, can be used directly
rstk.tar
- Polynomial solver. This VHDL package synthesizes to a FPGA implementation for a polynomial solver.
gtkwave-3.3.19.tar
- plesae fint the information
S1_38yima
- 可直接用于altera FPGA EP1C12仿真和下载使用 1、本程序模仿3/8译码器的功能 2、由拨码开关输入，led输出。-Can be directly used for simulation in altera FPGA EP1C12 1 3/8 decoder function 2 DIP switch input, led output.
S2_div
- 1、时钟分频，可以观看仿真波形 2、可以添加到硬件逻辑分析仪中观看波形-1, clock frequency divide, you can watch the simulation waveform 2, can be added to the hardware logic analyzer for waveform viewing
S3_WAVE
- 1、模拟正弦函数发生器 2、可使用逻辑分析仪查看波形 -1, analog sine function generator 2，logic analyzer can be used to view the waveform
S4_LCD_V
- 1、实现lcd显示的功能，基于alera FPGA EP1C12 2、可以显示预先定义好的数据-1, lcd display, based on alera FPGA EP1C12 2, pre-defined data can be displayed
S5_UART
- 1 基于altera FPGA EP1C12 实现UART传输功能-1 UART transmission function Based on altera FPGA EP1C12