资源列表
Verilog-dalianglic
- verilog大量例程，大家可以下载-verilog large number of routines, you can download to see
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
a-newmiller
- 一种改进的RFID中的密勒解码方法 使用verilog-RFID in an improved decoding method using verilog Miller
Staged-Output-Of-IJVM-By-VHDL
- IJVM by VHDL.IJVM is an instruction set architecture created by Andrew Tanenbaum for his MIC-1 architecture. It is used to teach assembly basics in his book Structured Computer Organization.
Auto_elect_ticket_machines
- 数字逻辑的自动电子售票机的quartus编程。-Digital logic quartus automatic electronic vending machine programming.
Horloge_1_A
- Timer vhdl 24hours with alarm_setup CDSE_powaa !
1-SDRAM
- 基于FPGA的SDRAM控制器的设计和实现源代码 -FPGA-based SDRAM controller design and implementation source code
FIFO
- 基于fpga的异步FIFO的设计和实现源代码-Fpga-based asynchronous FIFO design and implementation of source code
eytruytf.u
- implementation of median filter
TUSB9260
- Ti的USB3.0解决方案，基于TUSB9260，包含参考电路设计与应用指南。-Ti, USB3.0 solutions, based on the TUSB9260, including reference circuit design and application guide.
fifo_128x8x
- implementing first input fist output in vhdl
XilinxPlanAheadCourse
- xilinx官方推出的PlanAhead使用教程，适合xilinx FPGA开发人员参考学习。-use of the official launch of the PlanAhead xilinx tutorial reference for xilinx FPGA developers to learn.