资源列表
fir_filter
- finite impulse response filter verilog
121221
- 采用自然采样法写的spwm,此处用VHDL编写，区别以往的方法-Written by natural sampling spwm, here written with VHDL, the difference method of the past
cpu
- cpu design in verilog
DE3_usermanual
- ALTERA DE3用户文档资料，非常详尽，希望大家喜欢-ALTERA DE3 user documentation, very detailed, I hope you like it. . .
programs_examples
- 黑金开发吧，EP2C8Q208的相关原理图，及各个工程，直接打开就可使用-Development of black gold bar, EP2C8Q208 related schematics, and various works can be used to directly open. .
68013
- 使用68013的测试程序，包含68013固件程序-use of cy7c68013,data transfer from usb to pc.
FPGAlarge-scaledesign
- 利用 FPGA 实现大型设计时，可能需要FPGA 具有以多个时钟运行的多重数据通路，这种 多时钟FPGA 设计必须特别小心，需要注意最大时钟速率、抖动、最大时钟数、异步时钟 设计和时钟/数据关系。设计过程中最重要的一步是确定要用多少个不同的时钟，以及如何 进行布线，本文将对这些设计策略深入阐述。-Using FPGA to achieve large-scale design, may need to run the FPGA with multiple clocks to mult
ChipTrackLoop
- chip tracking loop in vhdl
FineMeasure
- a ranging fine measure function
CoarseMeasureSystem
- coarse measure in vhdl
counter
- counter in vhdl ... best fit
Actel_get_started_fusion
- Actel tipical get started project adapted for Fusion devices.