资源列表
SERIAL_CONTROLLER
- UART控制，使用三段式编写，非常规范，可以通过编译，仿真-UART transmission, the use of three-step preparation, very standard, you can compile, simulation
DE2_LCM_Ball
- Altera的DE2測試LCM用，不再只是初始設定，會有方塊圖型碰壁反彈的運動。-LCM with Altera' s DE2 test, not just the initial set into a wall will block diagram-based campaign rally.
decryption
- AES decryption in VHDL!! Wit LCD controls
Encryption
- AES implementation in VHDL!! Wit LCD controls-AES implementation in VHDL!! Wit LCD controls!!
8_Code
- AES algorithm encryption and display on FPGA spartran 2e
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
BPSK_Modulator
- IMPLEMENTATION OF BPSK MODULATOR IN FPGA
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
pc
- 程序计数器+地址寄存器，已预置一段mif文件，可实现加法运算。-Program Counter+ address register, a mif file has been preset, addition operations can be realized.
an500
- Altera官方网站提供的NANFLASH接口的设计文档，很实用。-Altera official website of the NANFLASH interface design documents, it is practical.
example_VHDL
- VHDL 语言的初级实例，27个。电子钟，mask，ask-VHDL, the primary instance, 27. Electronic clock, mask, ask ... ...