资源列表
lab1_Verilog
- verilog lab 是一个verilog 的实验文件，是初学者的学习材料。-verilog verilog lab is an experiment file, a beginner' s learning materials.
FSKmodemodulateVHDLprogramme
- FSK调制与解调的vhdl源代码与仿真指导，是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
lab1_VHDL
- lab VHDL for student enjoy it
8051core-Verilog
- 8051core-Verilog 为初学者提供便利资源-8051core-Verilog facilitate resources for beginners
8051core-Verilog
- 8051的verilog内核，fpga里实现8051的话用得上-8051 Verilog cores, fpga achieve useful 8051 words
ModelSim
- 完美版的 ModelSim视屏教程 欢迎学习ModelSim的下载-ModelSim ModelSimModelSimModelSimModelSim
FSKVHDL
- VHDL语言编写的程序，实现FSK调制与解调及仿真-VHDL prepared by the procedures, FSK modulation and demodulation and Simulation
3freqcount
- 高速而有效的实现频率计数器的控制器部分，整个工程全部上传-Upload all of the high-speed and efficient implementation of the controller portion of the frequency counter, the whole project
FSK_HDL
- 1. FSK调制VHDL程序 --文件名：PL_FSK --功能：基于VHDL硬件描述语言，对基带信号进行FSK调制 -1. FSK modulation VHDL procedures- File Name: PL_FSK- features: VHDL hardware descr iption language based on the base-band signal FSK modulation
51cpldDesignSource
- fpga+c51的设计源码，精品收藏,整个互联网都没有几个这样的源码推荐下载-fpga+ c51 design source, Collections.The Internet are not recommended several such source code download
taxi4
- 本程序是天华杯模拟题中出租车计价器源程序，由本人编写，经测试基本满足要求-This procedure is the day China Cup title in the taxi meter analog source, which I am prepared to meet the basic requirements have been tested
CompilerOptimizations
- To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level o