资源列表
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
dcfifo_design_example
- ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
VHDL
- 基于 VHDL平台 的NRZ码 转HDB3码 程序-NRZ-> HDB3 coding based on VHDL
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
FSMso-s3
- 有限状态机实现 自己做的 参考下-Finite state machine implementation
vga_principle
- vga显示原理与vga时序实现，doc格式，希望对大家有所帮助-vga vga display timing and realization of the principle, doc format, we hope to help
ISE_guide
- ISE使用指导，简单介绍了ISE的开发流程，pdf格式，希望对大家有帮助-ISE to use the guide, a brief introduction of the ISE' s development process, pdf format, we hope to help
FPGA_CLB
- FPGA可编程逻辑模块CLB的设计，pdf格式，希望对大家有帮助-FPGA programmable logic block CLB design, pdf format, we hope to help
XOR
- vhdl code for XOR gate
AND
- vhdl code for AND gate
RS_decode
- RS（204,188）译码，verlilog硬件描述语言的实现-rs decode
iic
- 跑马灯实验：利用计数器轮流点亮LED灯，实现各种动态效果。-Marquee experiment: the use of counter rotating light LED lights, to achieve a variety of dynamic effects.