资源列表
uart_R_S
- 用CPLD实现串口UART的收发功能，主要是时序的实现。晶振20MHz.-UART Serial Port with a CPLD to send and receive functions, mainly the timing of implementation. The device s Crystal is 20MHz.
Altera-CycloneII
- Protel99库_ALTERA Cyclone-Library _ALTERA CycloneII Protel99
SOPC_SOURCE_PROGRAM
- fpga各种源程序，C的形式。包含：lcd,led，ps2，jtag等等。-fpga variety of source, C form. Include: lcd, led, ps2, jtag and so on.
KTMTNC
- 5 lab organization computer
generator
- 信号发生器，用来产生输入的所要求的相应的信号并输出该信号。-Signal generator, used to generate the required input and output signals corresponding to the signal.
bin2bcd
- 用来将二进制的信号转化成BCD码形式的信号，用来在数码管上显示相应的数字。-To the binary signal into BCD code in the form of signals, used in the digital display the corresponding number.
CLK_DIV
- 用来产生一个电路的基准的时钟信号，并可以以此为基准产生其他与此时钟信号成倍数时钟信号-Used to generate a reference clock signal circuit and can produce this as a reference clock signal into the other and the clock multiplier
ModelSim2
- 利用Modelsim工具进行逻辑分析的教程，这是第二部分-Logic analysis tools using Modelsim tutorial, this is the second part of the
VHDLguoliangjiance
- 过零检测，输出部分有整数部分和偏移部分组成-Zero-crossing detection, the output part of the integer part and offset a part
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
5
- 基于SYSTEMVIEW的HDB3码编码器实验设计，看看吧-Based on the HDB3 Encoder SYSTEMVIEW experimental design and see for yourself