资源列表
XilinxFPGA(1-60)
- 系统地讲述了Xilinx FPGA的开发知识，包括FPGA开发简介，Verilog HDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISEd开发环境使用指南等-Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL La
clk
- 程序实现数码管日期显示（按键可控制月日、时分、分秒切换）和LCD显示-Program for digital date display (buttons can control the day, hours, minutes and seconds to switch) and LCD display
ic7
- 具有奇校验功能的串行数据发送电路，用状态机实现。-Functions with odd parity of serial data transmission circuit, with the state machine implementation.
EX2
- nios ii 嵌入式 实现数码管（按键切换）、LCD时间显示-nios ii embedded digital control implementation (key switch), LCD time display
verilog
- 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
spi_test
- VHDL ethernet implementation on FPGA
ipv4_packet_transmitter_latest.tar
- VHDL ethernet implementation on a FPGA
QAM16_demo
- This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xil
LinPF_RLS
- VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
LinPF
- This a VHDL module that implements linear prediction filter based on NLMS (normalized least mean square). The module takes complex signal as input and output comlex signal (real and imaginary). Tap size is 4, bit precision is set to 12 bits.-This i
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
CUDA-CPU-GPU
- 跟大家深入到CUDA的内部，为大家诠释为什么说：唯有NVIDIA CUDA才是终极的CPU-CUDA with you deep into the interior, as we interpret why: Only the CPU is the ultimate NVIDIA CUDA