资源列表
Erosion1
- 运用FPGA xilinx的system gennerator对图片进行腐蚀-Using the system gennerator FPGA xilinx corrosion images
conta_60
- vhdl count 60, kinda simple but i used it for a clock
ModelSim1
- 使用Modelsim用于逻辑分析设计的教程，这是第一部分-Analysis and design using the Modelsim tutorial for logic, this is the first part
sdram_controler
- sdram controler希望对大家有用啊-sdram controler
EZUSB_FirmwareDownload
- lsa fpga based. tested ,works good
freqdiv_simple
- frequency divider using VHDL quite simple expecially for beginners cheers
FPGA
- FPGA development vhdl
CPLD
- CCD开发板的CPLD图纸，使用XilinxCPLD，供大家参考-CCD CPLD development board drawings, with XilinxCPLD, for your reference
multiplier
- Moving panes can get confusing, and you may not always obtain the results you expect. Practice moving a pane around, watching the gray outline to see what happens when you drop it in various places. Your layout will be saved when you exit ModelSi
muhammadali_357
- T-flip flop lab done in our campus
guozhe_chuankou
- 串口接收程序,verilpog写的串口接收程序-receiver receiver chuankou
Module_6_VLSM_and_CIDR
- sach hay zo coi di maizo maizo