资源列表
UART_VHDL
- VHDL 实现 UART 全双工通讯，可以独立使能接收和发送，具有发送和接收完成标志位。-VHDL implementation of UART full duplex communication, can independently make can receive and transmit, with sending and receiving complete flag.
FPGA-based-display
- 基于FPGA的四位数字循环动态数码显示，内含100M分频器-FPGA-based digital loop two-digit display
dance-box
- 利用FPGA实现的跳舞机，有VGA的模块，二进制到BCD转换的模块等-Using FPGA to achieve Dance Dance Revolution, have VGA module binary to BCD conversion modules, etc.
taxi_THE-FINAL
- 基于FPGA的汽车计费系统，根据不同的情况会有不同的计费方式，基本能够符合实际情况-FPGA-based auto billing system, depending on the situation will be different billing methods, and can basically meet the actual situation
usb_sim_model
- EZ-USB的仿真模型，Verilog实现，能够实现端点传输，自用。-EZ-USB simulation model, Verilog implementation, to achieve the endpoint transmission, personal use.
i2c_slave
- Verilog实现的i2c从设备仿真模型，只需修改控制码就可直接使用，自用-Verilog implementations i2c slave device simulation models, simply modify the control code can be used directly, for personal use
M25P128_model
- M25P128（NOR FLASH）的仿真模型，Verilog实现，调试了很久才通，现在基本功能完整，仿真时打印调试信息，自用无问题。-M25P128 (NOR FLASH) simulation model, Verilog implementation, commissioning a long time to pass, and now the basic functions of a complete, print debug information during simulation,
jsq
- 基于FPGA的计算器，可以实现加减乘除运算功能，由于时间问题，浮点运算未能实现，其中的二进制与BCD码相互转换的模块可以使用-FPGA-based calculator, arithmetic calculation function can be achieved, due to time issues, floating-point operations failed to achieve, including binary and BCD code conversion modules t
nor_flash_core
- Verilog实现的NOR FLASH控制器，基于M25P128开发，功能完整，简洁易懂，自用无问题。-Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.
I2C
- Verilog语言实现I2C通信功能，可直接作为模块用于自己工程中。-Verilog language I2C communication functions can be used directly as a module for their own projects.
modulo-2^n-2^k-1-adder
- 用Verilong语言编写的模2^n-2^k-1加法器，该加法器多用于基于余数系统的蒙哥马利模乘运算。 -Implementation of modulo 2^n-2^k-1 adder Using Verilog.This adder can be use for RNS Montgomery Multiplication
IODELY
- Xilinx IO端口IODELY的使用例程。使用200M作为参考时钟。分别调用两组IODELY完成正向延时和等效逆向延时。-Xilinx IO port IODELY use routines. The use of 200M as a reference clock. Two groups of IODELY positive respectively call completion delay and the equivalent reverse delay.