资源列表
AsynCFIFO
- 跨时钟域，异步的FIFO，利用指针移动，数据不移动，通过两级锁存消除跨时钟域的信号竞争-Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch
phone
- 用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。-Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit bala
sinewave-case
- 利用verilog语言以及case语句实现正弦波波形，并利用modelsim完成波形仿真。-Use verilog language and case statement to achieve sinusoidal waveform, and use modelsim complete waveform simulation.
dierci
- 2011年电赛e题信号产生程序 产生10kbit/s -100Kbit/s的m序列 以及一个伪随机序列-M sequence 2011 CEC signal generator generates e title 10kbit/s - 100Kbit/s, and a pseudo-random sequence
AD9854_VHD
- 基于FPGA的AD9854的调试，可以产生最高120M频率的波形-Debug FPGA-based AD9854 can produce the highest frequency waveform 120M
ADC0809
- ADC0809芯片进行模数转换并将数值显示在共阴极数码管上-ADC0809 chip analog to digital conversion and the value displayed on the common cathode LED
DM9000A
- DM9000A 链接FPGA接口设计及NIOS驱动-DM9000A FPGA interface for NIOS timescope
pulse
- 一个产生可调频率和可调占空比Verilog源代码，希望对你起到作用-A variable frequency and variable duty cycle generates Verilog source code, you want to play a role
time60
- 一个占用资源很少的时钟产生Verilog代码，值得借鉴-A small footprint clock generator Verilog code, is worth learning
LCDandSDRAM-test
- 一个SOPC实验，关于LCD的控制和SDRAM的使用方法-A SOPC experiment on LCD of control and the use of SDRAM
MC8051_test
- 基于SOPC的MCU51单片机内核的开发，需要使用51单片机内核的直接拿走。-MCU51 microcontroller core based SOPC development, requires the use of 51 microcontroller core directly away.
MicroC-OSII-sopc
- MicroC-OSII 在SOPC环境下的搭建，程序已经搭建好一个Micro-OSII开发环境-MicroC-OSII built in SOPC environment, the program has set up a Micro-OSII good development environment