资源列表
x7seg
- 一个实用的FPGA数码管显示驱动，移植性比较好，Verilog语言编写，实测通过，可直接作为子模块调用-A practical FPGA digital display driver, portability is better, Verilog language, measured by, as a sub-module can directly call
pong
- Simple pong VGA game implemented in VHDL. It can be used as example for FPGA-programmers to show how handle VGA displaying with FGPA device.
BCD_2EX
- BCD-Excess3 transcoder described in VHDL language.
BCD_EXC3
- BCD-Exc3 code transcoder written in ABEL descr iption language
ChessClock
- Example of Chess Clock implementation in ABEL decription language.
PWMhuxideng
- VHDL语言编写的三总不同频率呼吸灯。使用PWM波控制呼吸频率。-VHDL language three total breathing light at different frequencies. Use PWM wave control breathing frequency.
smithwaterman
- 这个verilog代码实现的是DNA sequence alignment的功能-The verilog code is DNA sequence alignment function
8B-10B
- 8b10bencode bianmaqi -8b10bencode bianmaqi jiemaqi
quartus
- 流水灯状态机的一段式描述和二段式描述还有三段式描述的Verilog源码-Light water section of the state machine and the two-stage type descr iption descr iption descr iption of Verilog source code as well as three-
Ethernet-communication-VHDL-master
- Ethernet communication VHDL you can download it.
CPU
- 使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。-Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.
SERIAL-2-ETHERNET
- serial to ethernet converter