资源列表
bits
- verilog语言，移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
freq
- verilog 编写的频率计 管脚绑定支持Xilinx Spartan6-verilog prepared frequency meter pin binding support Xilinx Spartan6
sata_phy_latest.tar
- 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
szz
- 基于CPLD的数字钟，用VHDL语言编写，数码管显示，可调时调分，具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
Digital-dynamic-display-FPGA
- 数码管动态显示 FPGA verilog 基本例程-Digital dynamic display FPGA
FPGA-PWM_LED
- FPGA 实现PWM控制LED的例程 具有参考意义-FPGA to achieve LED PWM control routine
des
- des algorithm Simple
image_ver_main
- The design of multi level sensor is mostly based on FSM controller-The design of multi level sensor is mostly based on FSM controller
parallel_prefix_flag
- design of parallel prefix adder in verilog
traffic_cntrl
- FSM based traffic light controller
DDSN
- quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
modelsim
- 一款用于扩频通信发射系统的CPLD程序，基本的QPSK调制-A used in spread spectrum communication system of CPLD program, basic QPSK modulation