资源列表
SegLed_DynamDisp
- 这个是传统的fpga的入门代码，关于数码管的驱动代码，非常适合新手学习-This is a traditional fpga entry code on the digital control of the driver code, very suitable for novices to learn
VGA
- VGA驱动源码，Verilog HDL代码，50Hz-VGA driver source code, HDL Verilog code, 50Hz
DE2_115_IR
- 红外无线发送接收的功能和介绍，包括英文注释，还有仿真，引脚绑定-Infrared wireless transmission and reception functions and presentation, including comments in English, as well as simulation, pin bindings
ren_tian_tang
- 详细介绍了通过FPGA实现经典的任天堂游戏，有详细的代码跟注释-Details of the realization of the classic Nintendo game by FPGA, a detailed code with comments
w1
- 基于VHDL语言编写的EDA程序，可试验大月小月，润年平年的自行进位，也可手动调时。-Based on EDA VHDL language program, you can test large Satsuki month, leap year self-carry average year, you can manually adjust the time.
szz
- 基于VHDL语言编写的EDA程序，可试小时分秒的自动进位，也可手动调时。-Based on Automatic carry EDA VHDL language program, you can try hour, minute and second, you can manually adjust the time.
X16
- 基于VHDL语言编写的EDA程序，可显示“北华航天”四个字，也可尽享扫平，也可手动调结。-Based on EDA VHDL language program, you can display North China Aerospace words, but also enjoy the swinger, it can also be manually adjusted knot.
pinlv
- 基于VHDL语言编写的EDA程序，用数码管显示，频率大小。数字精确到0.1 -Based on EDA VHDL language program, with a digital display, frequency size. Digital precision to 0.1
mul
- vhdh code for modified multiplier in advanced mathematics
dds
- 这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
DDS
- Verilog实现DDS线性调频，Verilog实现DDS线性调频-Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM
UART_proj
- 串口发送接受功能，上位机发送消息给FPGA，FPGA接收后将相同的消息发送至上位机。-A serial port to send in function, PC sends a message to the FPGA, FPGA after receiving the same message is sent first place machine.