资源列表
image_combine_v
- 用于在FPGA中实现图像叠加字幕，字符为FPGA内部rom存储的点阵。-combine word on video stream in FPGA
mode_det
- 用于检测时钟的有无，通过输出的信号电平进行指示-For detecting the presence or absence of the clock, by the output signal level is indicated
eth_test_xps
- 基于xilinx SOC的SDK工程和最小系统ip核，可用于以太网测试，使用LWIP协议栈-The SDK works on xilinx SOC and minimum system ip nuclear, can be used for Ethernet testing, use LWIP Stack
GEN_HDMI
- 基于XILINX SOC的HDMI配置的SDK工程和IP核，用于HDMI芯片的配置-XILINX SOC based on the HDMI configuration SDK engineering and IP cores for HDMI chip configuration
hdmi_xps
- 基于XILINX SOC的HDMI配置最小系统IP核和SDK工程，用于进行HDMI芯片的配置-Configuring an HDMI chip XILINX SOC minimum system configuration of HDMI IP core and SDK works for
CRC16_V
- 基于Verilog的CRC16实现，已在altera FPGA验证通过-Based on the CRC16 Verilog implementation, has been verified in FPGA Altera.
Timing_Analysis_in_Quartus
- 影响FPGA设计中时钟因素,Quartus中的延时分析-Timing Analysis in Quartus
transmit
- vhdl实现1Hz发射桥路控制信号，设有死区时间。-vhdl achieve 1Hz emission control signal bridge, with a dead time.
pwmtransmit
- 利用SPWM的控制方式实现1hz方波信号，也可用于电机驱动。-Use SPWM control method to achieve 1hz square wave signal, it can also be used for motor drive.
acounter
- 利用VHDL语言设计的等精度数字频率计，有各个模块的详细设计语言，已调试成功。-The use of VHDL language design digital frequency meter, a detailed design language of each module has been successful debugging.
SRC_2CH
- 2通道HDCVI视频光端机：实现两个高速AD转换采集HDCVI信号，编码扰码后通过光纤远距离传输，对端收到后解码通过高速DA转换为HDCVI信号。-2 channel HDCVI video Guangduan Ji: two high-speed AD acquisition signal conversion HDCVI, scrambling code via the optical fiber remote transmission, receives an end after deco
multiplieranddivider
- 乘法器和除法器的VHDL实现方法,可运行，占用逻辑资源少。-VHDL descritpion about muiltiplier and divider