资源列表
parafac
- matlab parafac仿真 多维矩阵分解的算法-matlab parafac matrix decomposition algorithm for multi-dimensional simulation
Papilio_One_Verification
- Papilio_One_Verification 测试代码-Papilio_One_Verification test code
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
tdm_latest[1]
- TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换-TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
Dice_game
- VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
spi_sendbyte
- spi_sendbyte 用于发送SPI数据的控制-spi_sendbyte used to send data on the control of SPI
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
CRC32
- 基于FPGA平台的用verilogHDL设计的CRC32模块-a code for CRC32 based on FPGA by verilogHDL
DM9000Aethnet
- 国内重点大学使用最广泛的FPGA开发板-DE2板中经常使用的ip核——DM9000A-University of the domestic focus of the most widely used FPGA development board-DE2 board frequently used ip core- DM9000A
TLC5510
- 在超声波流量计中，能进行高速的ad采样，以达到ad转换的目的-In ultrasonic flowmeter, the ad can be sampled at high speed to achieve the purpose of ad conversion
Electronic-Clock_1.11
- 用quartusii 设计的电子钟原型文件-Electronic clock with quartusii prototype file design
CPLD-CRACK-SIEMENS-200PLC
- 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the