资源列表
ieee-std-1364
- 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
verilog2000
- verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
Verilog HDL Examples
- verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)
fpga学习中常用的缩略语
- fpga学习中常用的缩略语-commonly used abbreviations
max2work
- verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table
MYCPU2.0
- 用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
flowadd
- verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
custom_mul
- vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier
cuart
- verilog编写的全功能串口-verilog programme of serial port
percent
- verilog编写的计算百分比模块-Verilog prepared by calculating the percentage module
pipe
- verilog编写的流水线模块-Verilog modules prepared by the Pipeline