资源列表
hheev
- Consider shadow rain attenuation and multipath effects Particle image segmentation and matching subroutines themselves are prepared, Modulated signals to calculate its density Pu-related.
kyxvd
- Import data files as input parameters matlab program is running, This function is used to calculate the arbitrary function of the first order partial derivative (numerical methods), Is a two hidden layer back propagation neural network.
yv333
- STM32 all the information produced by the MP3, Correlation analysis process matlab method, matlab prepared cellular automata.
feng_ac88
- PV modules contain, MPPT module, BOOST module, inverter module, Dimensional phononic crystals FDTD method calculation examples band gap, The signal spectral analysis and filtering.
hiehoupei
- Rotating machinery 2-d holographic spectrum calculation, Pattern Recognition bayes discriminant analysis algorithm, Undergraduate complete set requirements refer to the standard test models.
piu_kf13
- Prediction Error Method for Parameter Identification - the idea of relaxation, Phased array antenna pattern (Chebyshev weights), There are detailed notes.
以太网控制器Verilog源码(含有MAC,MII接口)
- 以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
SD_rtl
- 用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
B4A_BluetoothExample
- cos tam nie wiem co spacja za malo liter 20
Vivado 2016.1 安装流程
- Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the of
Simple_RS232_UART.tar
- FPGA实现串口实例,实现串口的基本功能,(FPGA serial implementation examples)