资源列表
A4_Clock_Top
- 24小时制数字时钟，可自行调节时间，能暂停。(24 hours digital clock, can adjust time, can pause.)
A4_Uart_Top
- 提供一般FPGA开发板的Uart通讯协议(Provides the Uart communication protocol for the general FPGA development board)
蓝牙程序
- sdaddaddadacaczccsdDDAFCAFAFA(ascacaavavavaDADASDAFAVAVVA)
四通道DDS信号发生器
- 四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
UART_FPGA
- 使用VHDL写的UART收发模块，测试功能正常(Using VHDL to write the UART transceiver module)
async_counter_verilog
- 这是用verilog 实现的同步计数器。(this is a code for synchronous counter written in verilog.)
dq054
- Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. Principal component analysis model for establishing, PSS primary synchronization signal in the time domain simulation related.
VGA RefComp
- vga显示源码，官方提供示例，有vhdl基础的人更容易看懂，刚学习vhdl会偏难(VGA display source code, the official example, there are VHDL based people easier to understand, just learning VHDL will be difficult)
ekwgd
- Signal Processing ESPRIT method, Dual-line interpolation FFT harmonic analysis kaiser windows, Least-squares algorithm to fit a three-dimensional plane.
hm012
- Clustering analysis based on Euclidean distance, Achieve a grayscale image and further control for video surveillance, Noisy pulse correlation detection signal.
uikuh
- Mainly for data analysis and statistics, Prediction Error Method for Parameter Identification - the idea of relaxation, Classic GLCM texture calculation method.
verilog.tar
- please check the english descr iption.(an counter example written by verilog.)