资源列表
adc
- 用verilog实现TLC549——AD采集实验，采集完的数送给数码管显示-TLC549- AD Acquisition experimental collection finished with verilog number sent to the digital tube display
test_sdram
- 测试sdram程序,用来驱动sdram ip 核的程序-test sdram
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
dma_performance_demo_x8
- dma_performance_demo_x8.zip
wavegenerator
- 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verif
turbo
- turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
netfpga_full_3_0_0.tar
- 斯坦福大学的netfpga最新源代码开发包，用于开发网络路由器交换机等-Stanford University netfpga the latest source code development kit for developing network switches routers
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
hdlc
- HDLC接口协议的FPGA实现使用verilog-design of HDLC
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能，源码包括控制AD7606进行AD转换，其次实现FT3数据的传输，包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding
rgb2yuv
- 用VHDL和verilog编写的RGB颜色空间到YUV颜色空间的转换程序, 是FPGA视频处理中的常用程序!-Written in VHDL and verilog using RGB color space to YUV color space conversion process is commonly used in video processing FPGA program!
plj
- 数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA