资源列表
VHDLplj
- (1)设计4位十进制频率计测量范围: 1Hz～9999Hz (2）测量的数值通过4个数码管显示 (3）频率超过9999Hz时，溢出指示灯亮，可以作为扩大测量范围的接口-(1) the design of four decimal frequency measuring range: 1Hz ~ 9999Hz (2) measurement values through four digital tube display (3) the frequency of more than 999
PWM
- 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
vga
- 使用方法： vga编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: vga programming, copied to the hard drive, open the project file with ISE can
canbus
- 使用方法： canbus编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: canbus programming, copied to the hard drive, open the project file with ISE can
ByteBlasterII_en
- ALTERA下载线信息 快点下载吧 有用-ALTERA download line information quickly download it useful
DE2_CCD_PIP
- 摄像头采集数据的程序代码，使数据图像在屏幕中显示出来的程序。-Camera data acquisition program code, so that data images shown on the screen procedures.
xilinx_ise_9.x
- 《xilinx_ise_9.x_fpga_cpld设计指南》，光盘源文件- Xilinx_ise_9.x_fpga_cpld Design Guide, the source file CD-ROM
DDS
- 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
CPLD_Config
- 用Altera CPLD做为控制器从Flash上读取image文件对Altera FPGA编程-Altera CPLD used as a controller to read image from the Flash on the Altera FPGA programming
minicore
- minicore为一个加法器的最小结构，含有移位RAM 和调试的TB 程序等。-minicore for a minimum adder structure, containing translocation TB of RAM and debug procedures.
745221frequency
- 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
KEYBOARD
- vhdl语言编写的电子密码锁的键盘程序，本源码复制在word中，请黏贴到MAXPLUS等相应软件下运行-VHDL language electronic locks the keyboard program, the source copy of the word, please stick to the appropriate software, such as MAXPLUS run