资源列表
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
io_lvds
- xilinx LVDS接口程序,xilinx LVDS接口程序-xilinx LVDS interface program,xilinx LVDS interface program
UART_SUCCESS
- 实现FPGA和上位机的串口通信，里面由波特率发生器，移位寄存器，计数器，detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function bl
Disturb
- 适用于初学者的一个m序列扰、解码器-Apply to beginners as a sequence of interference m, the decoder
ff_mul
- 伽勒华域乘法器用于RS编码中，用verilogHDL语言实现-Galle Hua domain multiplier for RS encoding, the implementation language used verilogHDL
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
traffic_controller
- it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
statment
- 在VHDL的设计中用for 语句来实现2 个8 位数的相乘计算。-In the VHDL design using for statement to achieve two-digit multiplication calculation 8.
sd_card
- 在开发FPGA上比较有用，主要关于SD CARD的源码-FPGA in the development of more useful, the main source of about SD CARD