资源列表
sevenvote
- 本设计师一个7人表决器，用7个开关作为7个输入变量，输入变量是 1 时表示赞同，输入变量为 0 时表示不赞同。-The designer of a voting machine 7 with 7 switch 7 as input variables, input variables is a' 1 ' when agreed input variables for the' 0' that do not agree with.
verilog-Perl-3.120.tar
- Verilog Parser in Perl
vhdl
- 抢答器里的基本原程序,抢答模块，计时器电路JSQ的VHDL源程序，译码器电路YMQ的VHDL源程序-VHDL
CPLD_CODE
- CPLD的小程序集合，VHDL语言描述，可直接用quartus打开-CPLD collection of small programs, VHDL language descr iption can be directly opened with quartus
FPGA_Design_experience
- 讲解了在FPGA中时序设计时应该注意的问题，并分享了设计经验-On timing in the FPGA design should pay attention to the issue and to share the experience of the design
VHDL_VerilogHDL
- VHDL与Verilog语言的简明教程，介绍了用这两种语言进行硬件设计的基本方法与思路。-VHDL and Verilog language concise tutorial on using both hardware design language of the basic methods and ideas.
CPLD_CD
- 《CPLD开发实例》的配套光盘文件，包含大量的CPLD小程序，用VHDL语言描述-" CPLD development of examples of" CD-ROM of supporting documents, including a large number of small procedures CPLD, VHDL language used to describe
Ctl_LCD
- 采用FPGA控制LCD。程序中用了两个状态机-FPGA to control the use of LCD. Procedures with two state machine
vhdl_programs
- This the course for VHDL programming-This is the course for VHDL programming
calculator_vhdl
- Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB. -Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB.
VHDLtraining
- VHDL语言入门教学，比较全。适合入门的人看。-VHDL training
can_verilog
- 基于verilog开发的 ｃａｎ 接口 ＩＰ 核已经调试通过附有说明-can ip