资源列表
verilog_HDL_examples
- 本书介绍了大量verilog HDL程序设计的实例，对于verilog语言学习者和从事相关工作的工程师来说，都有一定的学习和参考价值。-The book introduced the verilog HDL programming a large number of examples, the verilog language learners and engineers engaged in related work both in terms of learning and a certai
DE2_NIOS_DEVICE_LED
- Altera FPGA 上利用nios嵌入式处理器实现USB的通信控制-Altera FPGA embedded processor nios use USB communication to achieve control
direct_implementation
- VHDL 实现 有限冲击响应滤波器的设计（直接式）-VHDL realization of finite impulse response filter design (direct)
distributed_implementation
- VHDL 实现 有限冲击响应滤波器的设计（分布式）-VHDL realization of finite impulse response filter design (distributed)
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计（串行式）-VHDL realization of finite impulse response filter design (Serial)
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
FirFilter
- 对称型线性相位FIR滤波器的VHDL源程序，比直接型FIR滤波器速度快一半-VHDLSourceProgramofFirFilter
div8
- 分频系数为8，分频输出信号占空比为50 的分频器-Frequency factor of 8, sub-frequency output signal duty cycle to 50 of the prescaler
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
adder
- 一个verilog的源码程序，用于加法器实验程序-A source of verilog procedures, experimental procedures for the adder
VCollide201
- 模型冲突检测，是VCollide的压缩文件。能够检测虚拟物体是否发生碰撞，并返回信息-Model of conflict detection is VCollide the compressed file. Can detect whether a collision between virtual objects, and return information
i2c
- i2c数据传输总线接口的verilog源程序-i2c bus interface procedures verilog