资源列表
mydds_rom
- 自己在参加altera NIOSii 软核设计大赛时编写的一个ip核，用于产生频率可调的正弦波-Their participation in the design of soft-core altera NIOSii the preparation of a competition when nuclear ip, used to generate the sine wave frequency adjustable
Statemachinedesigntechniques
- 老外写的编写有限状态机的书，书中提供的各种技巧，方法对大家肯定很有帮助-The preparation of a foreigner to write finite state machine of the book, the book provides a variety of techniques, methods to be helpful, I am sure you
examples
- Verilong 经典例子 王金明：《Verilog HDL 程序设计教程》-Wang Jinming Verilong classic example: " Verilog HDL Design Tutorial"
servo_module_worked
- verilog pwm to control servo motor on quartus
cascaded_adder
- implementation of cascade adder with verilog plus testbench
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
i2c
- I2C协议verilog源码，包含完整的测试代码及设计文档。-Verilog source I2C protocol, including the complete test code and design documents.
bios
- 系统BIOS的VHDL设计与实现，可在FPGA上验证，对小型系统的可靠性有深刻的认识。-System BIOS Design and Implementation of VHDL, the FPGA can be verified, for small systems have a deep understanding of reliability.
mario
- game in vhdl ( mario)
Digitalclocksignal
- 数字时钟信号用vhdl语言描述的源代码他光放利用到各个电路中-Vhdl digital clock signal with the source code language to describe his use of light to release all circuits
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
yetert
- This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).