资源列表
FPGA_SPI_Trans
- FPGA模拟SPI与MSP430通讯Verilog程序-A verilog program of fpga talks to mcu msp430 using spi
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
74LV245
- VHDL语言是面向硬件的语言，非常重要的文件-VHDL language is the language of the hardware-oriented
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
vhdl
- full adder is implemented using VHDL
mux
- Mulriplexer is implemented using VHDL.
jkff
- JK flip-flop is implemented using VHDL
srff
- SR flip flop is implemented using VHDL
shujujiegou
- 数自逻辑实验报告有关于83译码器的编写，用VHDL编写程序-Since the logic of the report of the number of experiments on the preparation of 83 decoder using VHDL programming
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure