资源列表
sdram32
- DDR SDRAM source verilog source codes
Testbenching-Example
- FPGA设计测试用例介绍PPT文档，对于初写测试用例很有帮助。-FPGA Design of test cases to introduce PPT files, helpful for the beginning of writing test cases.
zlg_avalon_lcd128_64
- 基于avalon的12864液晶模块ip核-The 12864-based LCD module avalon nuclear ip
fulladder4
- VHDL图形文件实现的4位全加器，希望对大家有用！-VHDL graphics files to achieve four full adder, in the hope that useful!
vhd2vl
- VHDL to verilog converter
Vhdl1
- Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below wo
fir-vhdl-code
- FIR FILTER CODE with VHDL
50602
- vhdl语言实现电子时钟设计 时分秒 可以设置-vhdl language designed to achieve accurate electronic clock can be set
ic6821_latest.tar
- vhdl core of IC6821 code
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code.
spiflashcontroller_latest.tar
- This VHDL module implements a state controller for a serial (SPI) Flash ROM
FPGA5
- 此为用VHDL语言基于FPGA开发板的分频器源程序-This is the FPGA using VHDL language development board based on the source of the prescaler