资源列表
VHDlzhilingdaquan
- vhdl 指令和库文件 大全 vhdl 指令和库文件 大全 vhdl 指令和库文件 大全 -vhdl command and library file vhdl Guinness Book instructions and library files and library files vhdl directive vhdl Guinness Book instructions and library files and library files vhdl directive vh
boxin
- 基于DDS的正弦波形发生器频率在DAC芯片速度的的情况下可以实现大范围的连续可调-FPGA
BIN_BCD
- 用硬件描述语音实现二进制数据转换成BCD数据-Using hardware descr iption voice to achieve the binary data into BCD data
freq_count
- 用硬件描述语言实现测量各种信号频率的功能-Using hardware descr iption voice to achieve the functions of measuring frequency
time_count
- 用硬件描述语言实现测量各种信号的周期的功能-Hardware descr iption language used to achieve a variety of signal measurement cycle value
FSK_FPGA
- FSK模拟信号源，利用ISE7.1或以上环境打开。-FSK signal simulator.The project can be open in ISE7.1 or upgrade version.
steppermotordrive
- Stepping Motor Driver Logic with VHDL.
Actel_Igloo_nano_UART
- This FPGA project include a simple version of the UART for Actel Igloo nano.
edaVHDL
- 数字系统与VHDL程序设计语言 非常高速硬件描述语言, 也就是一种硬件(数字电路)设计语言. 其最大特点是对电路的行为与结构进行高度抽象化规范化，并对设计进行模拟验证与综合优化，使分析和设计高度自动化。 -Digital systems with VHDL programming language very high speed hardware descr iption language, which is a hardware (digital circuit) design langu
fpgaverilog
- 使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可。-Use: 1. Copy to your hard disk. 2. With ISE to create items to the various code files, you can.
1
- VHDL语言在电路设计中的优化 vhdl语言，毛刺，状态机-VHDL language in the optimization of circuit design in vhdl language, burr, state machine
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- FPGA设计中几个基本问题的分析及解决 多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the d